1. Field of the Invention
This invention relates generally to the field of computer processors. More particularly, the invention relates to a method and apparatus for stacking a plurality of cores.
2. Description of the Related Art
Server processors include multiple product variants with a different number of compute cores and various amounts of L3 cache. For example, current server processors under development have three different die (15, 10 and 6 cores) and six different packages. Each die requires a separate tapeout and subsequent steppings, while each package requires a separate design and qualification effort. Finally, keeping all of these product variants in inventory and matching them with the actual demand carries a significant overhead.
At the same time, there is a need for even more specialized processors that meet specific workload requirements by combining different compute units on a single ring/mesh interface and unified L3 cache. Some processor customers require graphics units to support intensive computations, while others would like accelerators to be integrated for frequently executed functions, or a field-programmable gate-array (FPGA) to allow them to customize the server with their own logic design.
Some processor customers (e.g., in the high-performance computing market) prefer fewer cores that run at higher frequencies with the largest available L3 caches. To satisfy this market, a large number of cores (e.g., 15→6 cores) may be disabled on high core count (HCC) processors. While a small number of these parts are recovered from the units with defective cores, a significant amount of good cores are wasted by being permanently disabled.